1. Field of the Invention
The present invention relates to a semiconductor device and a method for forming the same, and in particular, to a semiconductor device having a shallow trench isolation (STI) structure and a method for forming the same.
2. Description of the Related Art
A power management integrated circuit (PMIC) is presently primarily applied to bipolar-CMOS (complementary metal oxide semiconductor transistor)-LDMOS (lateral diffused metal oxide semiconductor transistor) (BCD) structures. Complementary metal oxide semiconductor (CMOS) transistors may be used in digital circuits, bipolar transistors may be used for driving high current, and lateral diffused metal oxide semiconductor (LDMOS) transistors have high voltage (HV) handling capacity. The trends of power saving and high speed performance affect the structure of the LDMOS transistor. LDMOS transistor structures with lower leakage and on-resistance (RDSon) have been developed by semiconductor manufacturers.
The LDMOS devices are developed in various structures or by increasing the device size thereof to withstand a high off-state breakdown voltage. However, since the device size is increased, it is hard to reduce the on-resistance of the conventional LDMOS devices. RDSon is an important factor which affects the power consumption of the conventional LDMOS device. Therefore, the conventional LDMOS devices have a high on resistance to drain-source breakdown voltage ratio (Bvdss) (Ron/BVdss ratio), thereby affecting the reliability of the BCD processes.
Thus, a semiconductor device and a method for forming the same are desired to solve the aforementioned problems.